High density interconnects is an important design in the fabrication of printed circuit boards with through-holes. Miniaturization of these devices relies on a combination of thinner core materials, reduced line widths and smaller diameter through-holes. The diameters of the through-holes range from 75 μm to 125 μm. Filling the through-holes by copper plating has become more and more difficult with higher aspect ratios. This results in larger voids and deeper dimples. Another problem with through-hole filling is the way they tend to fill. Unlike vias which are closed at one end through-holes pass through a substrate and are open at two ends. Vias fill from bottom to top. In contrast, when through-holes are being filled with copper, the copper tends to begin to deposit on the walls at the center of the through-hole where it plugs at the center forming “butterfly wings” or two vias. The two vias fill to complete the deposition of the holes. Accordingly, the copper plating baths used to fill vias are not typically the same as are used to fill through-holes. Plating bath levelers and other bath additives are chosen to enable the right type of fill. If the right combination of additives is not chosen then the copper plating results in undesired conformal copper deposition. FIG. 1 is a diagram of current density (ASD) versus time in minutes of conventional direct current application to a substrate for filling through-holes. Cathodic current is applied to the substrate. Current density is applied for a given period of time such as for 100 minutes without changing the current density until the through-holes are filled.
Often the copper fails to completely fill the through-hole and both ends remain unfilled. An incomplete through-hole fill with copper deposit in the center with unfilled ends is sometimes referred to as “dog-boning”. The open spaces at the top and bottom of the holes are referred to as dimples. Entire dimple elimination during through-hole filling is rare and unpredictable. Dimple depth is perhaps the most commonly used metric for quantifying through-hole fill performance. Dimple requirements depend on through-hole diameter and thickness and it varies from one manufacturer to another. In addition to dimples, gaps or holes referred to as voids may form within a copper through-hole fill. Larger dimples affect further processing of the panel and larger voids affect device performance. An ideal process completely fills through-holes with a high degree of planarity, i.e., build up consistency, without voids to provide optimum reliability and electrical properties and at as low as possible a surface thickness for optimum line width and impedance control in an electrical device.
In order to address the foregoing problems the industry typically uses two different electroplating baths when attempting to plug and fill through-holes. A first copper bath is used to fill the through-holes until the two vias are formed in the through-holes as mentioned above. A second bath having a substantially different formulation specifically directed to filling vias replaces the first bath to complete the filling process. However, this process is both time consuming and inefficient. The through-hole filling process must be closely monitored to gauge the time when the first bath must be replaced with a via filling bath. Failure to change baths at the correct time typically results in dimple and void formation. Moreover, using two distinct plating baths for a single process increases the cost to both the manufacture and the customer. The plating process must be stopped to change the baths, thus further reducing the efficiency of the process.
In addition, the thickness of substrates such as printed circuit boards is increasing. Many conventional printed circuit boards now have a thickness exceeding 100 μm. While conventional direct current plating has been successful in providing acceptable through-hole fill under some circumstances for printed circuit boards having a thickness of 100 μm or less, attempts to fill through-holes in boards with thickness ranges exceeding 100 μm such as 200 μm and greater has been less than satisfactory. Often, the through-holes have unacceptable amounts of dimples exceeding 10 μm in depth and average void areas in the through-holes in excess of 10% to 15%.
Another problem encountered in metal plating is the formation of nodules on the metal deposit. Nodules are believed to be crystals of the metal being plated and grow out of the plated surface. Nodules may range in diameter from less than 1 micron to as large as several millimeters. Nodules are undesirable for a variety of electrical, mechanical, and cosmetic reasons. For example, nodules are readily detached and carried by cooling air flows into electronic assemblies, both within and external to electronic article housings, where they may cause short-circuit failure. Therefore, the nodules have to be removed before the plated substrates are assembled into electronic articles. Conventional methods of removing the nodules involve laser inspection of each metal plated substrate followed by manual removal of the nodules by workers using microscopes. Such conventional methods leave room for worker error and are inefficient.
Accordingly, there is a need for a method to improve through-hole filling of substrates such as printed circuit boards.